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INTEGRATED CIRCUITS
DATA SHEET
74LVC1G00 Single 2-input NAND gate
Product specification Supersedes data of 2000 Nov 08 File under Integrated Circuits, IC24 2001 Apr 05
Philips Semiconductors
Product specification
Single 2-input NAND gate
FEATURES * Wide supply voltage range from 1.65 to 5.5 V * High noise immunity * Complies with JEDEC standard: - JESD8-7 (1.65 to 1.95 V) - JESD8-5 (2.3 to 2.7 V) - JESD8B/JESD36 (2.7 to 3.6 V). * 24 mA output drive (VCC = 3.0 V) * CMOS low power consumption * Latch-up performance 250 mA * Direct interface with TTL levels * Inputs accept voltages up to 5 V * SOT353 package. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH PARAMETER propagation delay inputs A and B to output Y CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 k VCC = 2.5 V; CL = 30 pF; RL = 500 VCC = 2.7 V; CL = 30 pF; RL = 500 VCC = 3.3 V; CL = 50 pF; RL = 500 VCC = 5.0 V; CL = 50 pF; RL = 500 CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. input capacitance power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2 DESCRIPTION
74LVC1G00
The 74LVC1G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. This feature allow the use of these devices in a mixed 3.3 and 5 V environment. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging current backflow through the device when it is powered down. The 74LVC1G00 provides the single 2-input NAND function.
TYPICAL 3.3 2.2 2.6 2.2 1.8 5 14 ns ns ns ns ns
UNIT
pF pF
2001 Apr 05
2
Philips Semiconductors
Product specification
Single 2-input NAND gate
FUNCTION TABLE See note 1. INPUT A L L H H Note 1. H = HIGH voltage level; L = LOW voltage level. ORDERING INFORMATION PACKAGE TYPE NUMBER 74LVC1G00GW PINNING PIN 1 2 3 4 5 B A GND Y VCC SYMBOL data input B data input A ground (0 V) data output Y supply voltage DESCRIPTION TEMPERATURE RANGE -40 to +85 C PINS 5 PACKAGE SC-88A MATERIAL plastic B L H L H
74LVC1G00
OUTPUT Y H H H L
CODE SOT353
MARKING VA
handbook, halfpage
B1 A2 GND 3
MNA096
5 VCC
handbook, halfpage
1 2
B A
00
4 Y
Y
4
MNA097
Fig.1 Pin configuration.
Fig.2 Logic symbol.
2001 Apr 05
3
Philips Semiconductors
Product specification
Single 2-input NAND gate
74LVC1G00
handbook, halfpage
1 2
handbook, halfpage
&
B Y
4
MNA098
A
MNA099
Fig.3 IEE/IEC logic symbol.
Fig.4 Logic diagram.
RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr,tf (t/f) PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall times VCC = 1.65 to 2.7 V VCC = 2.7 to 5.5 V active mode VCC = 0 V; Power-down mode CONDITIONS 0 0 0 -40 0 0 MIN. 1.65 5.5 5.5 VCC 5.5 +85 20 10 MAX. V V V V C ns/V ns/V UNIT
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO ICC, IGND Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC =0 (Powered-down mode), the output voltage can be 5.5 V in normal operation. 3. Above 55 C the value of PD derates linearly with 2.5 mW/K. 2001 Apr 05 4 PARAMETER supply voltage input diode current input voltage output diode current output voltage output source or sink current VCC or GND current storage temperature power dissipation per package for temperature range from -40 to +85 C; note 3 VI < 0 note 1 VO > VCC or VO < 0 active mode; notes 1 and 2 VO = 0 to VCC CONDITIONS - -0.5 - -0.5 - - -65 - MIN. -0.5 -50 +6.5 50 VCC + 0.5 +6.5 50 100 +150 200 MAX. +6.5 V mA V mA V V mA mA C mW UNIT
Power-down mode; notes 1 and 2 -0.5
Philips Semiconductors
Product specification
Single 2-input NAND gate
DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH HIGH-level input voltage VCC (V) MIN. 1.7 2.0 0.7 x VCC - - - - - - - - - VCC - 0.1 1.2 1.9 2.2 2.3 3.8 - - - Tamb (C)
74LVC1G00
-40 to +85 TYP.(1) - - - - 0.7 0.8 0.3 x VCC 0.1 0.45 0.3 0.4 0.55 0.55 - - - - - - 5 10 10 - - - - - - - - - - - - - - - - - - - 0.1 0.1 0.1 MAX.
UNIT
1.65 to 1.95 0.65 x VCC - 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5
V V V V V V V V V V V V V V V V V V V A A A
VIL
LOW-level input voltage
1.65 to 1.95 - 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5
0.35 x VCC V
VOL
LOW-level output voltage
VI = VIH or VIL; IO = 100 A VI = VIH or VIL; IO = 4 mA VI = VIH or VIL; IO = 8 mA VI = VIH or VIL; IO = 12 mA VI = VIH or VIL; IO = 24 mA VI = VIH or VIL; IO = 32 mA
1.65 to 5.5 1.65 2.3 2.7 3.0 4.5
VOH
HIGH-level output VI = VIH or VIL; IO = -100 A 1.65 to 5.5 voltage 1.65 VI = VIH or VIL; IO = -4 mA VI = VIH or VIL; IO = -8 mA VI = VIH or VIL; IO = -12 mA VI = VIH or VIL; IO = -24 mA VI = VIH or VIL; IO = -32 mA 2.3 2.7 3.0 4.5 3.6 0 5.5
ILI Ioff ICC Note
input leakage current power OFF leakage current quiescent supply current
VI = 5.5 V or GND VI or VO = 5.5 V VI = VCC or GND; IO = 0
1. All typical values are at VCC = 3.3 V and Tamb = 25 C.
2001 Apr 05
5
Philips Semiconductors
Product specification
Single 2-input NAND gate
AC CHARACTERISTICS GND = 0 V; tr = tf 2.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS tPHL/tPLH propagation delay inputs A and B to output Y see Figs 5 and 6 VCC (V) 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 AC WAVEFORMS MIN. 1.0 0.5 0.5 0.5 0.5
74LVC1G00
Tamb (C) -40 to +85 TYP. 3.3 2.2 2.6 2.2 1.8 MAX. 8.0 5.5 5.8 4.7 4.0 ns ns ns ns ns UNIT
handbook, halfpage
VI VM
A, B input GND
t PHL VOH Y output VOL VM
t PLH
MNA611
INPUT VCC 1.65 to 1.95 V 2.3 to 2.7 V 2.7 V 3.0 to 3.6 V 4.5 to 5.5 V VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V 0.5 x VCC VCC VCC 2.7 V 2.7 V VCC VI tr = tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns 2.5 ns
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.5 Inputs A, B to output Y propagation delay times.
2001 Apr 05
6
Philips Semiconductors
Product specification
Single 2-input NAND gate
74LVC1G00
handbook, full pagewidth
VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL
MNA616
VCC 1.65 to 1.95 V 2.3 to 2.7 V 2.7 V 3.0 to 3.6 V 4.5 to 5.5 V
VI VCC VCC 2.7 V 2.7 V VCC
CL 30 pF 30 pF 50 pF 50 pF 50 pF
RL 1 k 500 500 500 500
VEXT tPLH/tPHL open open open open open tPZH/tPHZ GND GND GND GND GND tPZL/tPLZ 2 x VCC 2 x VCC 6V 6V 2 x VCC
Definitions for test circuits: RL = Load resistor. CL = Load capacitance including jig and probe capacitance (see Chapter "AC characteristics"). RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.6 Load circuitry for switching times.
2001 Apr 05
7
Philips Semiconductors
Product specification
Single 2-input NAND gate
PACKAGE OUTLINE Plastic surface mounted package; 5 leads
74LVC1G00
SOT353
D
B
E
A
X
y
HE
vMA
5
4
Q
A
A1
1
e1 e
2
bp
3
wM B detail X Lp
c
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E (2) 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1
OUTLINE VERSION SOT353
REFERENCES IEC JEDEC EIAJ SC-88A
EUROPEAN PROJECTION
ISSUE DATE 97-02-28
2001 Apr 05
8
Philips Semiconductors
Product specification
Single 2-input NAND gate
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
74LVC1G00
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2001 Apr 05
9
Philips Semiconductors
Product specification
Single 2-input NAND gate
Suitability of surface mount IC packages for wave and reflow soldering methods
74LVC1G00
SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
2001 Apr 05
10
Philips Semiconductors
Product specification
Single 2-input NAND gate
DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS
74LVC1G00
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2001 Apr 05
11
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For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2001
Internet: http://www.semiconductors.philips.com
SCA 72
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/02/pp12
Date of release: 2001
Apr 05
Document order number:
9397 750 07974

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